Vik

Samsung’s Gear S2 Classic 3G and 4G Smartwatches with eSIM to Hit the Market in March
  • Comments are Closed

Samsung’s Gear S2 Classic 3G and 4G Smartwatches with eSIM to Hit the Market in March

Samsung has revealed that its Gear S2 Classic 3G and 4G smartwatches, which were formally introduced last September, will be available in the U.S. on March 11, 2016. The new wearable gadget will be able to connect to the Internet without a smartphone nearby and will no longer be just an addition for handsets, but a completely autonomous device. It will also be one of the first devices to feature eSIM (embedded SIM) compatible with multiple operators.

The US versions of Samsung Gear S2 Classic 3G/4G with eSIM are using the Qualcomm Snapdragon 400 SoC, and although there are many variants of the Snapdragon 400, it would seem this one is a dual-core Krait 200, although we are still waiting for confirmation on the matter. Known specifications show the device running at 1 GHz, coupled with Adreno 305 graphics and integrated baseband capabilities. The smartwatch is equipped with 512 MB of RAM, 4 GB NAND flash storage, 300 mAh battery as well as 3G/4G, 802.11 b/g/n Wi-Fi, Bluetooth 4.1 and NFC wireless technologies. The wearable gadget sports accelerometer, gyroscope, heart rate, ambient light and barometer sensors to enable various health/fitness tracking applications. The Gear S2 Classic features 1.2-inch circular display with 360×360 resolution (302 ppi density). Like the rest members of the Gear family, the S2 Classic 3G runs Samsung’s proprietary Tizen operating system. The 4G variant is identical to the 3G variant, but for US markets only, and so it’s still just HSPA+ rather than LTE.

Unlike Samsung’s contemporary smartwatches without eSIM functionality, the Samsung Gear S2 Classic with eSIM models feature a speaker in addition to two microphones. The new wearable will be able to make calls, send text messages and emails as well as receive notifications without connectivity to any smartphone. While using the phone function of the smartwatch may not be very convenient (besides, a person talking to their watch seems a little weird), quick email bylines and responses on the wrist make a lot of sense. Moreover, the integration of eSIM into a watch is another step towards integration of certain smartphone functionality into wearable devices.

The eSIM is a GSMA-approved standard for embedded SIM cards that cannot be removed from a device and which are compatible with multiple operators. In theory users can choose their preferred carriers, although in this case the standard only supports one carrier at a time and it’s not clear if users will be able to change the one originally stored. The Samsung Gear S2 Classic 3G in the U.S. will be compatible with AT&T, T-Mobile and Verizon. In other countries, there will be different operators: Samsung has worked with M1 Limited, Orange, Singtel, StarHub, Telefónica, TeliaSonera and Vodafone Group, so, the new Gear S2 Classic 3G will be available in multiple countries. The 4G variant will be available only in the US.

Samsung has not yet announced an official MSRP for its flagship smartwatch, however Verizon has started taking pre-orders for the watch, pricing it at $399 off-contract, which amounts to a $50 premium over the regular Gear S2 Classic.

Images by Samsung and Stolen Girlfriends Club/Lucire.com

ARM Announces Cortex-A32 IoT and Embedded Processor
  • Comments are Closed

ARM Announces Cortex-A32 IoT and Embedded Processor

Today ARM announces the new Cortex A32 ultra-low power/high efficiency processor IP. For some readers this might come as a surprise as it’s only been a few months since we saw the announcement of the Cortex A35 which was presented as a replacement for the Cortex A7 and A5, so this leaves us with the question of where the Cortex A32 positions itself against both past IPs such as the A7 and A5, but also how it compares against the A35.

The answer is rather simple: It’s still a replacement for the A7 and A5, but targets even lower power use-cases than what the A35 was designed for. While ARM sees the A35 as the core for the next billion low-end smartphones, the A32 seems to be more targeted at the embedded market. In particular it’s the “Rich Embedded” market that ARM seems to be excited about. The differentiation lies between use-cases which require a full-fledged MMU and thus able to run full operating systems based on Linux, and those who don’t and could make due with a simpler micro-controller based on one of ARM’s Cortex-M profile IPs. It’s also worth to mention that although last time we claimed that the A35 would servce the IoT market, ARM seems to see wearables and similar devices as part of the “Rich Embedded” umbrella-term and thus now it seems more likely that it’s the A32 that will be the core that will power such designs.

This leads us to the mystery of what exactly is the A32? During the briefing the only logical question that seemed to come to mind is: “Is this an A35 with 64-bit ‘slashed off‘?” While ARM chuckled at my oversimplification, they agreed that from a very high-level perspective that it could be considered as an accurate description of the A32.

In more technical terms, the A32 is an 32-bit ARMv8-A processor with largely the same microarchitectural characteristics of the Cortex A35. As a reminder to our readers out there: The ARMv8 ISA is not only an 64-bit instruction set but also contains many improvements and additions to the 32-bit profile commonly named as AArch32. Among the larger differences between the A35 and A32 is that the latter’s microarchitecture has been tuned and optimized to achieve the best performance and efficiency for 32-bit.

Indeed, performance wise, the A32 is advertised as being able to match the Cortex A35.  The improvements lie in power efficiency: as a result of dropping its 64-bit capabilities, the new core is now able to achieve up to 10% better efficiency than the Cortex A35. Similarly to the A35, the A32 promises to achieve vastly superior performance per clock versus the Cortex A5 and A7, achieving anywhere from a 31% increase in integer workloads to a massive factor of 13x in crypto workloads, which the A32 is still capable of as they’re included in the AArch32 ARMv8 profile.

While only a few months ago the Cortex A35 was advertised as ARM’s smallest Cortex-A core, this title has now been passed on to the A32. ARM claims the core is around 30% smaller than the A35; The decrease in size, mostly due to the slimming down of the micro-architecture due the removal of 64-bit capability, allows the Cortex A32 to scale down to <0.25mm² in its smallest configuration, a significant decrease compared to the A35’s disclosed <0.4mm². The core remains as configurable as the Cortex A35, able to run as either as single core or any as a cluster up to four cores. Optionally vendors can also configure cache sizes, with L1 ranging from 8KB to 32KB and L2 either being completely absent to up to 1MB in size.

ARM’s philosophy of “having the right design for the job” now seems more apparent than ever as we see an steadily increasing portfolio of processor IPs specialized for different use-cases. The A32 seems to fit right in with this strategy and we’ll more than certainly see a large array of devices powered by the core in the future to come.

ARM Announces Cortex-A32 IoT and Embedded Processor
  • Comments are Closed

ARM Announces Cortex-A32 IoT and Embedded Processor

Today ARM announces the new Cortex A32 ultra-low power/high efficiency processor IP. For some readers this might come as a surprise as it’s only been a few months since we saw the announcement of the Cortex A35 which was presented as a replacement for the Cortex A7 and A5, so this leaves us with the question of where the Cortex A32 positions itself against both past IPs such as the A7 and A5, but also how it compares against the A35.

The answer is rather simple: It’s still a replacement for the A7 and A5, but targets even lower power use-cases than what the A35 was designed for. While ARM sees the A35 as the core for the next billion low-end smartphones, the A32 seems to be more targeted at the embedded market. In particular it’s the “Rich Embedded” market that ARM seems to be excited about. The differentiation lies between use-cases which require a full-fledged MMU and thus able to run full operating systems based on Linux, and those who don’t and could make due with a simpler micro-controller based on one of ARM’s Cortex-M profile IPs. It’s also worth to mention that although last time we claimed that the A35 would servce the IoT market, ARM seems to see wearables and similar devices as part of the “Rich Embedded” umbrella-term and thus now it seems more likely that it’s the A32 that will be the core that will power such designs.

This leads us to the mystery of what exactly is the A32? During the briefing the only logical question that seemed to come to mind is: “Is this an A35 with 64-bit ‘slashed off‘?” While ARM chuckled at my oversimplification, they agreed that from a very high-level perspective that it could be considered as an accurate description of the A32.

In more technical terms, the A32 is an 32-bit ARMv8-A processor with largely the same microarchitectural characteristics of the Cortex A35. As a reminder to our readers out there: The ARMv8 ISA is not only an 64-bit instruction set but also contains many improvements and additions to the 32-bit profile commonly named as AArch32. Among the larger differences between the A35 and A32 is that the latter’s microarchitecture has been tuned and optimized to achieve the best performance and efficiency for 32-bit.

Indeed, performance wise, the A32 is advertised as being able to match the Cortex A35.  The improvements lie in power efficiency: as a result of dropping its 64-bit capabilities, the new core is now able to achieve up to 10% better efficiency than the Cortex A35. Similarly to the A35, the A32 promises to achieve vastly superior performance per clock versus the Cortex A5 and A7, achieving anywhere from a 31% increase in integer workloads to a massive factor of 13x in crypto workloads, which the A32 is still capable of as they’re included in the AArch32 ARMv8 profile.

While only a few months ago the Cortex A35 was advertised as ARM’s smallest Cortex-A core, this title has now been passed on to the A32. ARM claims the core is around 30% smaller than the A35; The decrease in size, mostly due to the slimming down of the micro-architecture due the removal of 64-bit capability, allows the Cortex A32 to scale down to <0.25mm² in its smallest configuration, a significant decrease compared to the A35’s disclosed <0.4mm². The core remains as configurable as the Cortex A35, able to run as either as single core or any as a cluster up to four cores. Optionally vendors can also configure cache sizes, with L1 ranging from 8KB to 32KB and L2 either being completely absent to up to 1MB in size.

ARM’s philosophy of “having the right design for the job” now seems more apparent than ever as we see an steadily increasing portfolio of processor IPs specialized for different use-cases. The A32 seems to fit right in with this strategy and we’ll more than certainly see a large array of devices powered by the core in the future to come.